Scientists from the Institute of Computing Technology of the Chinese Academy of Sciences (CAS) have presented an improved 256-core multi-chip computing complex and plan to scale it to a 1600-core chip that uses the entire plate as a single computing device.
Increasing the density of transistors with each new generation of chips is becoming more and more difficult, so chip manufacturers are looking for other ways to improve the performance of their processors, including architectural innovations, large crystal sizes, multi-chip designs, and even scaling wafers into chips. The latter are currently being created only by Cerebras, but it seems that Chinese developers are also looking at this technology. Apparently, they have already created a 256-core multi-chip circuit and are exploring ways to scale the wafer, using the entire wafer to create one large chip.
Scientists from the Institute of Computing Technologies of the Chinese Academy of Sciences presented an improved 256-core multi-chip computing complex called Zhejiang Big Chip. The multichiplet design consists of 16 chiplets containing 16 RISC-V cores each and connected to each other in a conventional symmetric multiprocessor (SMP) manner using an on-chip network so that the chiplets can share memory. Each chiplet has several inter-chip interfaces to connect to neighboring chiplets via a 2.5D interposer and the researchers say the design scales to 100 chiplets or up to 1600 cores.
Zhejiang chipsets are manufactured using a 22 nm process technology, presumably by Semiconductor Manufacturing International Corp. (SMIC). It is unknown how much energy a 1600-core assembly connected to each other using an intermediate device and manufactured at a 22-nm production site will consume. However, as The Next Platform notes, nothing prevents CAS from creating a 1600-core wafer-sized chip that significantly optimizes power consumption and performance by reducing latency.
The researchers note that multi-chip designs can be used to create processors for exaflop supercomputers, which is what AMD and Intel are doing today. "For current and future exaflop computing, we predict that the hierarchical architecture of the chiplets will become a powerful and flexible solution," the researchers write. "The hierarchical architecture of the chiplets is designed as a set of cores and a set of chiplets with a hierarchical connection. Inside the chiplet, the cores exchange data using an ultra-low latency interconnect, while a low latency connection occurs between the chiplets, which is an advantage of advanced packaging technology, so that the delay inside the chiplet and the NUMA effect in such a highly scalable system can be minimized." Meanwhile, CAS researchers suggest using a multi-level memory hierarchy for such assemblies, which could potentially cause difficulties with programming such devices.
"The memory hierarchy includes main memory, embedded and off—chip memory," the description says. "The memory of these three levels varies in bandwidth, latency, power consumption and cost. In the overview of the hierarchical chiplet architecture, several cores are connected via a cross-switch and use a common cache. The module is connected to each other via a network inside the chiplet. Several modules form a chiplet, and the chiplet is connected to each other through a network between the chiplets, and then connected to external memory. Careful design is necessary to make full use of such a hierarchy. "Making reasonable use of memory bandwidth to balance the workload of various computing hierarchies can significantly improve the efficiency of a chiplet system. Proper design of communication network resources can ensure that chiplets perform tasks with shared memory together."